1. Field of the Invention
The present invention relates to a memory circuit being capable of a compression test, and more particularly to a memory circuit having a higher degree of compression for the compression test in the memory configuration corresponding to multiple bit inputs/outputs.
2. Description of the Related Art
For memory circuits such as semiconductor memories, the segment configuration and column decoder configuration in a memory bank are designed considering the input/output bit configuration. For example, a memory device has a configuration such that 8-bit read data is output simultaneously and 8-bit write data is input simultaneously. In a case of such a multiple bit input/output configuration, the memory device has a number of common data buses corresponding to the number of inputs/outputs in order to output read data simultaneously and to input write data simultaneously to the plurality of common data bases. As a result, read or write is executed simultaneously from the input/output circuits corresponding to the number of inputs/outputs.
In a test of a memory circuit, a compression read test is executed for a plurality of sense amplifiers selected by a same column select signal, by simultaneously writing a same data (H level or L level) and simultaneously reading the same data. This test is to check whether the basic writing and reading operation to a memory cell is executed normally for a large capacity memory cell, and the time required for the test can be decreased by executing the test for a plurality of sense amplifiers simultaneously.
FIG. 1 is a drawing depicting a conventional compression read test. In FIG. 1, eight segments, SGM 0-7, disposed in a memory bank, are shown. In these eight segments, four segment select signals, cac0z-cac3z, generated by the first stage column decoder cacdec, are supplied to a group of four segments, SGM0-3 and SGM4-7, respectively. The segment select signals, cac0z-cac3z, are supplied to the column decoder C/Dec in the respective segment via the pre-column decoder pcdec of the respective segment. The column decoder C/Dec selects one of the 64 column select signals, CL0-63. And the signals of the four global data bus lines for reading rgdb0x/z-rgdb3x/z, selected by one column select signal, are amplified by the four sense buffers SB in the segment, and read data buses for testing trdb0x/z and trdb3x/z connected to these sense buffers are driven. x in each signal and bus indicates activation at L level, and z indicates activation at H level. Therefore, the read data bus for testing trdb0x/z is comprised of a pair of buses which output reverse phase signals. This is the same for the other read data bus for testing trdb3x/z.
FIG. 2 is a circuit diagram of the first stage column decoder cacdec in a prior art. The first stage column decoder in FIG. 2 has four NAND gates, 51-54, and two inverters, 55 and 56. The two column address signals, ca06z and ca07z, and the bank select signal, cbnk0z, are supplied, the column address signals are set to be reverse phase signals by the inverters 55 and 56 respectively, and combinations of the four column address signals in total are supplied to the NAND gates 51-54. The bank select signal cbnk0z is supplied to the NAND gates 51-54.
In the first stage column decoder, one of the four segment select signals, cac00x-cac03x, becomes activation level (L level) according to the combination of column addresses when the bank select signal cbnk0z is at H level. These segment select signals, cac0x-cac3x, are inverted by the inverter 18 shown in FIG. 1, becomes segment select signals cac0z-cac3z having a reverse phase, and are supplied to the pre-column decoder pcdec of each segment.
In FIG. 1, two segments out of the eight segments are selected and activated when one of the four segment select signals, cac0x-cac3x, is activated (L level). In the example in FIG. 1, the segment select signal cac3z becomes activation level (H level), and two segments, SGM3 and SGM7, are selected and activated (Active). As a result, eight read data in total, that is, read data from four sense buffers SB of the segments SGM3 and SGM7 respectively, are supplied to the eight input/output circuits, and are output from the input/output terminals in parallel via the common data bus lines, which are not illustrated.
Such a configuration is based on the consideration that multiple bits are simultaneously input/output. In other words, two segments in a bank are simultaneously selected for a predetermined column address, and eight read data are simultaneously output to respective sense buffers. And eight read data is simultaneously output from the eight input/output terminals via corresponding eight common data buses and input/output circuits.
The compression read test is executed for the above mentioned column decoder and segments which are structured according to the read mode. The compression read test is a test to judge whether the read data from the plurality of memory cells are all the same or are partially different, and output the result from the test terminal. This makes read judgment easier and decreases the time required for a read test.
For this compression read test, the first common read data bus for testing trdb0x/z is disposed for the first segment group SGM0-SGM3, and the second common read data bus for testing trdb3x/z is disposed for the second segment group SGM4-SGM7. By supplying a predetermined column address just like the above mentioned read operation, one segment in the first and second groups is activated respectively. And outputs from the four sense buffers SB in the segment SGM3, for example, are supplied to the first common read data bus for testing trdb0x/z simultaneously. Outputs from the four sense buffers SB in the segment SGM7, for example, are supplied to the second common read data bus for testing trdb3x/z simultaneously. As a result, a read test can be executed for the eight sense buffers SB simultaneously.
Since in the conventional configuration, multiple bits are input/output, a plurality of common data buses are disposed and a plurality of read data is simultaneously output by a normal read operation. Therefore in the compression read test, data read simultaneously are all processed to match or mismatch signals by the common read data buses for testing trdb0x/z and trdb3x/z, and are output.
However, the simultaneous read test is executed only for eight memory cells, so the compression rate is not very high. Even though one memory bank has eight segments, only two of these eight segments are activated in a selected memory bank, therefore the remaining six segments must be tested at another time by setting the memory banks continuously at a selected status. This makes the efficiency of a compression read test poor.
With the foregoing in view, it is an object of the present invention to provide a memory circuit which can increase the efficiency of a compression read test.
It is another object of the present invention to provide a memory circuit which can increase the efficiency of a compression read test by enabling an operation which is different from a normal read operation.
To achieve the above objects, an aspect of the present invention is a memory circuit which selects N number of segments out of M number of segments (N less than M) during normal reading, wherein all the M number of segments are activated during a read test in order to drive a common data bus for testing by a plurality of sense buffers in the M number of segments. For this, test signals are supplied to a column decoder, and segment select signals, for activating the M number of segments, are generated in response to the test signal. In this way, a plurality of segments in a memory bank in a select status can be simultaneously selected to execute a read test, and the efficiency of a compression read test can be improved.
To achieve the above objects, another aspect of the present invention is a memory circuit comprising: M number of segments (M is an integer) each of which has a plurality of memory cells; and a common data bus for testing arranged for the M number of segments, wherein N number of segments out of the above M number of segments (N is an integer, N less than M) are activated during normal reading, and all the above M number of segments are activated during a compression read test in order to drive the common data bus for testing by a plurality of sense buffers in the M number of segments.
According to a preferred embodiment of the present invention, the memory circuit further comprises a column decoder for generating a segment select signal for the above segments by decoding the column address signal, wherein the above column decoder is supplied with a compression test control signal, and generates a segment select signal for simultaneously activating the above M number of segments, regardless the above column address signal, when the compression test control signal is in active status.
Another preferred embodiment of the present invention is a memory circuit wherein the above M number of segments are divided into L groups (L is an integer), the common data bus for testing is commonly disposed for the M/L number of segments of each group, one segment out of the M/L number of segments of each group is selected during the above mentioned normal reading, and the M/L number of segments of each group are simultaneously activated during the compression read test in order to supply data to the above common data bus for testing.